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Macros</h2></td></tr>
<tr class="memitem:ga2bb7416cfd483de37442d6c4db638cf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xadcps__v2__2.html#ga2bb7416cfd483de37442d6c4db638cf6">XAdcPs_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;(Xil_In32((BaseAddress) + (RegOffset)))</td></tr>
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<tr class="memitem:ga48770272099dfc236414809f6ac0f911"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xadcps__v2__2.html#ga48770272099dfc236414809f6ac0f911">XAdcPs_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;(Xil_Out32((BaseAddress) + (RegOffset), (Data)))</td></tr>
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<tr class="memitem:gadaffb0cadf00238070668f65b9854573"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xadcps__v2__2.html#gadaffb0cadf00238070668f65b9854573">XAdcPs_FormatWriteData</a>(RegOffset,  Data,  ReadWrite)    </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Register offsets of XADC in the Device Config</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The following constants provide access to each of the registers of the XADC device. </p>
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<tr><td colspan="2"><div class="groupHeader">XADC Config Register Bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">XADC Interrupt Status/Mask Register Bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The definitions are same for the Interrupt Status Register and Interrupt Mask Register.</p>
<p>They are defined only once. </p>
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<tr><td colspan="2"><div class="groupHeader">XADC Miscellaneous Register Bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">XADC Miscellaneous Control Register Bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Internal Register offsets of the XADC</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The following constants provide access to each of the internal registers of the XADC device. </p>
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<tr><td colspan="2"><div class="groupHeader">Configuration Register 0 (CFR0) mask(s)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Configuration Register 1 (CFR1) mask(s)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Configuration Register 2 (CFR2) mask(s)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Sequence Register (SEQ) Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">OT Upper Alarm Threshold Register Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">JTAG DRP Bit Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Unlock Register Definitions</div></td></tr>
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